Formal Synthesis of Digital Systemsf

An approach, called Formal Synthesis, to the design and ver-iication of digital systems is presented. Working in a goal-directed mode, and starting from a behavioural speciication, a user can interactively generate a design together with a proof of a theorem that asserts its correct-ness. The speciications are expressed in veritas + , a higher-order logic based on type theory. The resultant design may be directly translated into the model hardware description language. The system has been computa-tionally implemented and a simple example is given illustrating the process of formal synthesis.